Modern integrated circuits are getting more and more complex. In order to evaluate the functionality of integrated circuits various testing techniques were developed. One way to test the functionality of an integrated circuit uses scan chains. Scan chains include multiple components that are serially connected to each other during a scan mode of the integrated circuit. These scan chains are used to propagate test stimulations and test responses. The number of scan chains per integrated circuit is usually selected as a compromise between scan test speed (which requires more scan chains) and number of integrated circuit pins that are allocated for scan mode tests.
Some prior art scan method use a compactor (or compressor) that compresses scan chain test responses. The compression can be very effective in reducing the number of integrated circuit pins allocated for outputting scan chain test responses but is subject to the corruption of valid scan chain test responses by unknown or indefinite logical states. Various prior art compactors (including spatial compactors and temporal compactors) are illustrated in U.S. Pat. No. 6,829,740 of Rajski et al., and in U.S patent application serial number 2005/0055613A1 of Mitra et al. both being incorporated herein by reference.
In order to reduce the corruption of valid scan chain test responses a configurable mask can be used. The mask is configured by a multi-cycle configuration process during which mask configuration information serially propagates through the integrated circuit until reaching the configurable mask. This multi-cycle configuration process causes the configurable mask to mask valid scan chain test responses as well as indefinite scan chain test responses. If, for example, a mask is configured during x scan cycles, the k'th scan chain outputs an indefinite scan chain test response during the y'th scan cycle while outputting valid scan chain test responses during the next (x−1) scan cycles, then the configurable mask will mask the indefinite scan chain test response (during the y'th scan cycle) but also mask the valid scan chain test responses of the k'th scan chain that are outputted during the next (x−1) scan cycles.
There is a growing need to find effective devices and methods for testing a circuit.